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ETsac's avatar
ETsac
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7 years ago

Error message while trying to compile a project with one LVDS output.

Hi, i have been trying to test LVDS functionality by creating an output as reg (not wire) and then setting its' val with a non-blocking assignment inside an always loop. I started by creating a sin...
ETsac's avatar
ETsac
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7 years ago

Are you referring to the 2nd way of transferring the data from the ADC to the FPGA?

The ADC is the ADS4225. Link: http://www.ti.com/lit/ds/symlink/ads4225.pdf

See page 62 where the DDR LVDS output data is described. Both clock edges are used. The output data rate is twice (250MS/s) the ADC sampling rate (125MS/s) because you have 6 pairs that output 12 bits so data must be transmitted on both clock edges in order to do that.

See page 66 where multiplexed output transmission is described. The ADC has 2 channels and in order to transmit both of them through one output it has to double the bit rate from 250MS/s to 500MS/s.

Thanks again for your time.

Regards

Manos