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Altera_Forum's avatar
Altera_Forum
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17 years ago

Error from two signal going to one output

I'm trying to make a pair of tristate buffers that are switched by an input as shown in the included picture. My problem is that I'm getting an error that says I cannot send two signals to the same output. The thing is, there will only be one signal being sent at all times due to the inverter on one of the buffers.

Figure 3 in: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04542137

Ultimately I want to create a circuit as shown in Figure 4 of that paper.

I had to place LCELLs in the design so that Quartus doesn't optimize the design to a little knub.

http://img517.imageshack.us/img517/5683/tribuffersth5.png (http://imageshack.us)

tristate buffer code:

module Tristate (in, oe, out);

input in, oe;

output out;

tri out;

bufif1 b1(out, in, oe);

endmodule

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The buffers will have slightly varying delay in them, and depending on the enable bit, one of these delays will be propagated. You can read the paper for more details on the overall design.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    that's interesting. Obviously quartus looks at the two drivers and ignores the inverter. May be you need to put a mux there?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The paper claims that tristete buffers work better than MUXes, so I'm trying it this way. I have tried MUXes in the past though.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I meant put a mux after tristate as well. But bear in mind that tristates are actually implemented as muxes inside fpgas except at io (generally speaking).

    Kaz
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    A mux is the solution, I agree with Kaz. The implementation suggested by the authors seems to me only a solution for ASIC design.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    In the FPGA, the tri-state buffer is the I/O cell, therefore you can't have anything in between a tri-state cell and the actual pin otherwise it will just get turned into a mux (as the other guys have suggested - internal tri-states are converted to muxes). Do you actually want the output to ever be tri-state? (this can't happen with your design as it is).

    --- Quote Start ---

    I had to place LCELLs in the design so that Quartus doesn't optimize the design to a little knub.

    --- Quote End ---

    What do you mean by "a little knub"?

    I would imagaine that with what you've got, the design would end up as one LE which effectively multiplexes your two signals. Why don't you want that?

    By the way, your link is to a login page.

    --- Quote Start ---

    The paper claims that tristete buffers work better than MUXes, so I'm trying it this way.

    --- Quote End ---

    Is the paper referring to ASIC or FPGA? There are quite a few things different between the two. (although I've only designed FPGAs myself). Perhaps think about the function in terms of I/O and timing rather than the nitty gritty.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I never heard that internal three-state buffers are available in ASICs, they surely don't exist in FPGA. The assumption, that three-state buffers have a better performance than multiplexers seems rather arbitrary to my opinion.

    There have been previous discussion about puf design in the forum before. As one point, it seems questionable if the accidental delay skew, that is utilized by this technique, has a considerable amount compared to systematic and reproducable routing delays.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Good morning! Sorry about the link to the paper, I will provide a working link ASAP.

    --- Quote Start ---

    What do you mean by "a little knub"?

    --- Quote End ---

    When I enter the design as shown in the paper and compile, it seems that Quartus II optimizes away all of the logic, except the IO stuff. When I use the "Locate" option when right-clicking on the delay part of my design or any of its sub-components, it says that it "Could not locate" the item in the floorplan. Maybe I'm just taking this wrong?

    Yes, I have asked about PUF design in these forums before. I brought it back up because I found this paper and wanted to try the new method. In my attempts to use multiplexers as delay elements, the design was also optimized away as I described earlier. I believe that VHDL has a syn_keep and keep attribute available so that I don't have to use LCELLs? Also, Xilinx FPGA apparently have something called a LOC attribute which are supposed to help with this aswell, but of course I'm working with Altera hardware and software so I don't know if the same attributes are available. What is the equivalent for verilog? I am not familiar enough with VHDL.

    Thanks for the replys!