Honored Contributor
Honored ContributorGood morning! Sorry about the link to the paper, I will provide a working link ASAP.
--- Quote Start --- What do you mean by "a little knub"? --- Quote End --- When I enter the design as shown in the paper and compile, it seems that Quartus II optimizes away all of the logic, except the IO stuff. When I use the "Locate" option when right-clicking on the delay part of my design or any of its sub-components, it says that it "Could not locate" the item in the floorplan. Maybe I'm just taking this wrong? Yes, I have asked about PUF design in these forums before. I brought it back up because I found this paper and wanted to try the new method. In my attempts to use multiplexers as delay elements, the design was also optimized away as I described earlier. I believe that VHDL has a syn_keep and keep attribute available so that I don't have to use LCELLs? Also, Xilinx FPGA apparently have something called a LOC attribute which are supposed to help with this aswell, but of course I'm working with Altera hardware and software so I don't know if the same attributes are available. What is the equivalent for verilog? I am not familiar enough with VHDL. Thanks for the replys!
