Error from two signal going to one output

In the FPGA, the tri-state buffer is the I/O cell, therefore you can't have anything in between a tri-state cell and the actual pin otherwise it will just get turned into a mux (as the other guys have suggested - internal tri-states are converted to muxes). Do you actually want the output to ever be tri-state? (this can't happen with your design as it is).

--- Quote Start ---

I had to place LCELLs in the design so that Quartus doesn't optimize the design to a little knub.

--- Quote End ---

What do you mean by "a little knub"?

I would imagaine that with what you've got, the design would end up as one LE which effectively multiplexes your two signals. Why don't you want that?

By the way, your link is to a login page.

--- Quote Start ---

The paper claims that tristete buffers work better than MUXes, so I'm trying it this way.

--- Quote End ---

Is the paper referring to ASIC or FPGA? There are quite a few things different between the two. (although I've only designed FPGAs myself). Perhaps think about the function in terms of I/O and timing rather than the nitty gritty.