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Hakim1's avatar
Hakim1
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2 years ago

Error during quartus simulation syntax error

Hi, i wrote my code for a 3 to 8 decoder in structural vhdl :

i had no problems during the compilation. When i tried to simulate to see the results, it says :

**** Running the ModelSim simulation **** c:/altera/13.1/modelsim_ase/win32aloem//vsim -c -do Laboratoire2.do Reading C:/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl # 10.1d # do Laboratoire2.do # ** Warning: (vlib-34) Library already exists at "work". # # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 # -- Compiling module DECODEUR_3_x_8 # # Top level modules: # DECODEUR_3_x_8 # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 # -- Compiling module DECODEUR_3_x_8_vlg_sample_tst # ** Error: Simulation_decodeur_3_x_8.vwf.vt(30): near ",": syntax error, unexpected ',' # ** Error: c:/altera/13.1/modelsim_ase/win32aloem/vlog failed. # Executing ONERROR command at macro ./Laboratoire2.do line 4 Error.

I never had this error before. I opened the file Simulation_decodeur_3_x_8.vwf.vt and i didnt see any errors. I uploaded the code of the decodeur and the simulation one. Can you help me ?

Simulation

2 Replies

  • Hakim1's avatar
    Hakim1
    Icon for New Contributor rankNew Contributor
    2 years ago

    i found the error. It seems to be the name that i gave to my inputs and outputs. when i changed "input" to "entree" and "output_0/7" to "sortie_0/7" it worked. i dont know why maybe input and output are key words that i cant use. Hope this helps for the others.

    • roeekalinsky's avatar
      roeekalinsky
      Icon for Contributor rankContributor
      2 years ago

      "input" and "output" are not reserved key words in VHDL, but they are in Verilog, and your test bench is written in Verilog.