Forum Discussion

Hakim1's avatar
Hakim1
Icon for New Contributor rankNew Contributor
2 years ago

Error during quartus simulation syntax error

Hi, i wrote my code for a 3 to 8 decoder in structural vhdl : i had no problems during the compilation. When i tried to simulate to see the results, it says : **** Running the ModelSim simul...
Simulation
Hakim1's avatar
Hakim1
Icon for New Contributor rankNew Contributor
2 years ago

i found the error. It seems to be the name that i gave to my inputs and outputs. when i changed "input" to "entree" and "output_0/7" to "sortie_0/7" it worked. i dont know why maybe input and output are key words that i cant use. Hope this helps for the others.

roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
2 years ago

"input" and "output" are not reserved key words in VHDL, but they are in Verilog, and your test bench is written in Verilog.