Error (12061): Can't synthesize current design -- Top partition does not contain any logic

Verilog that you feed into the synthesis tools needs to represent constructs that imply hardware (gates, registers, memory, etc).

You might start by reading this:

https://people.ece.cornell.edu/land/courses/ece5760/DE2/tut_quartus_intro_verilog.pdf

and this:

https://www.jameswhanlon.com/writing-synthesizable-verilog.html

If you had a module like this:

module top;
$write("Hello, world!");
endmodule

that is NOT a construct that can be synthesized into logic.

That kind of verilog code usually used for simulation purposes. Quartus is not a simulator tool, it Analyze & Synthesis code.

I believe the resources provided by ak6dn should be sufficient for you to learn.

Alternatively, you may checkout Nandland for beginner coding.

https://nandland.com/learn-verilog/

Have fun coding!

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

May I know do you need further help in regards to this case?

Best Regards,

Richard Tan

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.