Error (12061): Can't synthesize current design -- Top partition does not contain any logic

Verilog that you feed into the synthesis tools needs to represent constructs that imply hardware (gates, registers, memory, etc).

You might start by reading this:

https://people.ece.cornell.edu/land/courses/ece5760/DE2/tut_quartus_intro_verilog.pdf

and this:

https://www.jameswhanlon.com/writing-synthesizable-verilog.html

If you had a module like this:

module top;
$write("Hello, world!");
endmodule

that is NOT a construct that can be synthesized into logic.