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Amerakim's avatar
Amerakim
Icon for New Contributor rankNew Contributor
3 years ago

Error (12061): Can't synthesize current design -- Top partition does not contain any logic

Hello, I am fairly new to Verilog HDL and I started with trying to print out a simple "hello world". But when i tried to synthesize my code, the error " Top partition does not contain ant logic" pops...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

That kind of verilog code usually used for simulation purposes. Quartus is not a simulator tool, it Analyze & Synthesis code.

I believe the resources provided by ak6dn should be sufficient for you to learn.


Alternatively, you may checkout Nandland for beginner coding.

https://nandland.com/learn-verilog/


Have fun coding!


Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.