Error 10500: Syntax error

Question

Hey guys this is my third VHDL project so forgive me if the answer is obvious:

When I compile my code I get the message

Error (10500): VHDL syntax error at ts.vhd(28) near text "/="; expecting "!", or "=>"

in reference to this line

When (s0)/=lm then

in this code

LIBRARY IEEE;

USE ieee.std_logic_1164.all;

Entity ts is

PORT ( reset : in std_logic;

q, z: out std_logic_vector(2 downto 0));

end ts;

Architecture arc of ts is

Type st1 is (s0, s1, s2);

signal lm: st1;

Type st2 is (t0,t1,t2);

signal mn: st2;

Begin

Process (reset)

Begin

if (reset = '1') then

lm <= s0;

elsif (reset = '0') then

Case lm is

When s0 => lm <= s1 after 2000000000 ns;

When s1 => lm <= s2 after 1000000000 ns;

When s2 => lm <= s0 after 3000000000 ns;

End case;

Case mn is

When (s0)/=lm then

mn <= t0;

When (s1 or s2)/=lm then

mn <= t1 after 1999999999 ns;

When t1 => mn <= t2 after 999999999 ns;

end case;

End If;

End Process;

With lm Select

q <= "110" When s0,

"011" When s1,

"010" When s2;

With mn Select

z <= "110" When t0,

"011" When t1,

"010" When t2;

End arc;

any ideas?

altera_forum · Answer

The problem is that you can't use the inequality operator within your case choice.

The choice must be a term that can be equated to the case expression.

If you want to make assignments to mn dependent on the state of lm then you could have something like

case lm is

when s0 =>

mn <= to;

when s1 =>

mn <= t1 etc

altera_forum · Answer

Hello,

this my 1st project involve vhdl.this project,my supervisor wants me to use up3 board,receive 8 bit data from ADC, process it and display through visual basic(PC)..

this what i got so far..if the problems is too obvious,im still amateur bro..

1. i got error 10500 a lot

2. how to communicate up3 board using serial,did it still need vhdl code?

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity up3_board is

port( datain_adc: IN STD_LOGIC_VECTOR(7 downto 0);

clock: IN STD_LOGIC; -- Clock Input from Altera Board

dataout_serial: OUT STD_LOGIC_VECTOR(7 downto 0));

end up3_board;

architecture BEHAVIOR of up3_board is

IF RISING_EDGE(clock) THEN

PROCESS(clock,datain_adc)

BEGIN

if datain_adc='00000000'--data from ADC,not correct yet..

then

dataout_serial<="00000000";--serial output in binary..not correct yet

elsif datain_adc='00000001'

then

dataout_serial<="00010000";

elsif datain_adc='00000010'

then

dataout_serial<="00010101";

elsif datain_adc='00000011'

then

dataout_serial<="00010110";

elsif datain_adc='00000100'

then

dataout_serial<="00010111";

elsif datain_adc='00000101'

then

dataout_serial<="00011000";

elsif datain_adc='00000110'

then

dataout_serial<="00011001";

elsif datain_adc='00000111'

then

dataout_serial<="00011010";

elsif datain_adc='00001000'

then

dataout_serial<="00011010";

elsif datain_adc='00001001'

then

dataout_serial<="00011010";

elsif datain_adc='00001010'

then

dataout_serial<="00011010";

elsif datain_adc='00001011'

then

dataout_serial<="00011010";

end process;

end BEHAVIOR;

altera_forum · Answer

You can't have an if outside the process, and you are missing a few end if's

altera_forum · Answer

Hi :) , plz any one can till me where is the error :( :( in this code" for circual Shifting Lift", the message error is "Error (10500): VHDL syntax error at modm.vhd(10) near text "begin"; expecting "end", or a declaration statement"

and the secone one

"Error (10500): VHDL syntax error at modm.vhd(33) near text "begin"; expecting "end", or a declaration statement"

library ieee;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;

package crll is

function crl(s1:std_logic_vector;index:integer) return std_logic_vector;

end crll;

package body crll is

begin

process

function crl(s1:std_logic_vector;index:integer) return std_logic_vector is

variable z : std_logic_vector(s1'high downto s1'low);

begin

if(index >= s1'length) then

assert false

report "crl: rotate index is greater than variable length can't rotate" severity error;

end if;

if(index < 0) then

assert false

report "crl: rotate index is negative,can't rotate" severity error;

end if;

if(index = 0) then

z:=s1;

else

for jj in 1 to s1'high loop

z:= s1(s1'high-jj downto 0) & s1(s1'high downto s1'high-jj+1);

if(jj = index) then

exit;

end if;

end loop;

end if;

return z;

end crl;

begin

crl;

end process;

end crll;

altera_forum · Answer

Five lines in your code aren't legal VHDL syntax for a package and have to be removed (they are commented below): package body crll is 
--begin 
--process 
function crl(s1:std_logic_vector;index:integer) return std_logic_vector is end crl; 
--begin 
--crl;
--end process;
end crll;

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Error 10500: Syntax error

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