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Altera_Forum's avatar
Altera_Forum
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18 years ago

Error 10500: Syntax error

Hey guys this is my third VHDL project so forgive me if the answer is obvious: When I compile my code I get the message Error (10500): VHDL syntax error at ts.vhd(28) near text "/="; expecti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Five lines in your code aren't legal VHDL syntax for a package and have to be removed (they are commented below): 

package body crll is 
--begin 
--process 
function crl(s1:std_logic_vector;index:integer) return std_logic_vector is

end crl; 
--begin 
--crl;
--end process;
end crll;