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Honored Contributorhttps://www.alteraforum.com/forum/attachment.php?attachmentid=7080
Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition Info: Processing started: Mon Mar 25 17:47:55 2013 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DSP -c DSP Error (10500): VHDL syntax error at DSP.vhd(21) near text "PORT"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at DSP.vhd(21) near text ";"; expecting "<=" Info: Found 0 design units, including 0 entities, in source file dsp.vhd Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 222 megabytes Error: Processing ended: Mon Mar 25 17:47:56 2013 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings --------------------------------------------------------------------------------------------------------- hey guys i need yer help i don't know why these errors entered in this program and it driving me crazy is anybody here to help me and solve my problem and one more question. could answer this question which CPLD or FPGA used for Ghz frequency ? you make me glad if solve my problem thx a lot
