Error 10327: Can't determine definition of operator "+"

Besides other possible problems: Real is a VHDL type not supported for logic synthesis, e.g. as a variable or signal. It can be only used for compile time calculations.

The part of your code, that is actually performing floating point arithmetic (the 2.0**i doesn't) can be coded with IEEE float and respective multiply and divide MegaFunctions. But it's most likely better to design a suitable fixed point respresentation for the signals.

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Hi there everyone,

I'm new to VHDL and the Quartus software, and right now I have a project in which I need to detect the velocity and acceleration of a toy car that passes through 2 infrared LED detectors, which is all connected to the Altera DE2 board.

Now my friend and I wrote the code count the time for the car's body to pass through the first LED (sensor1) and the second LED (sensor2). Since we know the car's body length, and we know the time that the LED's are blocked, we can calculate the velocity of the car. We get 2 data: initial and final velocity.

Also we calculate the acceleration by subtracting the final velocity by the initial, then dividing it by the total it takes to go from 1st sensor to the 2nd.

The problem occurs when we compile it. The problem is when I want to make SecTmp1 : SecTmp1 + 2**i (exponent), which is basically converting from binary to decimal because t1 (the time the 1st sensor is blocked by the car) is stored in an array.

I've seen in this forum that Error 10327 occurs when a STD_LOGIC_VECTOR is added using '+', but in this case SecTmp1 is an integer, not an array... so I'm not sure how to tackle this problem.

Thanks for the help!

Here's the body of the code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

USE ieee.std_logic_unsigned.all;

ENTITY photosensei IS

PORT( a50MHz_clk, wipe_on1, wipe_on2 : IN STD_LOGIC;

wipe_off : OUT STD_LOGIC);

END photosensei;

ARCHITECTURE way OF photosensor IS

SIGNAL a2MHz_clk_count: std_logic_vector(19 downto 0);

SIGNAL a2MHz_clk : std_logic;

SIGNAL t1, t2, tt : std_logic_vector(19 downto 0);

VARIABLE seconds1, seconds2, secondst : REAL;

VARIABLE v1, v2, a : REAL;

--TYPE distance IS RANGE 0 TO 1000000

--UNITS

--mm;

--cm = 10 mm;

--m = 100 cm;

--km = 1000 m;

--END UNITS distance;

CONSTANT track_length : REAL := 0.038;

BEGIN

PROCESS --2MHz clock

BEGIN

WAIT UNTIL a50MHz_clk'EVENT AND a50MHz_clk = '1';

IF a2MHz_clk_count < X"19" THEN

a2MHz_clk_count <= a2MHz_clk_count + 1;

ELSE

a2MHz_clk_count <= X"00000";

a2MHz_clk <= NOT a2MHz_clk;

END IF;

END PROCESS;

PROCESS --time_1 and velocity_1 for when sensor 1 is blocked

VARIABLE SecTmp1 : REAL;

BEGIN

WAIT UNTIL wipe_on1'EVENT AND wipe_on1 = '1';--indicates when sensor1 is blocked and gives a 'high signal'.

loop_t1 : WHILE wipe_on1 = '1' loop

WAIT UNTIL a2MHz_clk'EVENT AND a2MHz_clk = '1';

t1 <= t1 + 1;

END LOOP loop_t1;

SecTmp1 := 0.0;

FOR i IN 0 TO 19 LOOP

IF t1(i) = '1' THEN

SecTmp1 := SecTmp1 + 2.0**i; - ERROR HERE

END IF;

seconds1 := SecTmp1;

v1 := track_length/seconds1;

END LOOP;

END PROCESS;

PROCESS --time_2 and velocity_2 for when sensor 2 is on

VARIABLE SecTmp2 : REAL;

BEGIN

WAIT UNTIL wipe_on2'EVENT AND wipe_on2 = '1'; --indicates when sensor2 is blocked and gives a 'high signal'.

loop_t2 : WHILE wipe_on2 = '1' loop

WAIT UNTIL a2MHz_clk'EVENT AND a2MHz_clk = '1';

t2 <= t2 + 1;

END LOOP loop_t2;

SecTmp2 := 0.0;

FOR i IN 0 TO 19 LOOP

IF t2(i) = '1' THEN

SecTmp2 := SecTmp2 + 2.0**i;

END IF;

seconds2 := SecTmp2;

v2 := track_length/seconds2;

END LOOP;

END PROCESS;

PROCESS --total time from sensei 1 to sensei 2

VARIABLE SecTmpt : REAL;

BEGIN

WAIT UNTIL wipe_on1'EVENT AND wipe_on1 = '1';

loop_tt : WHILE wipe_on2 = '0' loop

WAIT UNTIL a2MHz_clk'EVENT AND a2MHz_clk = '1';

tt <= tt + 1;

END LOOP loop_tt;

SecTmpt := 0.0;

FOR i IN 0 TO 19 LOOP

IF tt(i) = '1' THEN

SecTmpt := SecTmpt + 2.0**i;

END IF;

secondst := SecTmpt;

END LOOP;

END PROCESS;

PROCESS (v1, v2, secondst) --acceleration

BEGIN

a := (v2-v1)/secondst;

END PROCESS;

END way;

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Hi,

first of all you have a typo in the name of your entity ( photosensei ?). Next point is that

you could not use non-constant real values for synthesis. No synthesis tool is able to convert such value into logic. Real number could be used in simualtion only. I'm not a VHDL expert, but I think you have also a problem with the variable definitons of "seconds1, seconds2, secondst", because they are defined outside of the processes which are using it.

Kind regards

GPK

Hello everyone, I think there's one more strange construction in the code:

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WAIT UNTIL wipe_on1'EVENT AND wipe_on1 = '1';--indicates when sensor1 is blocked and gives a 'high signal'.

loop_t1 : WHILE wipe_on1 = '1' loop

WAIT UNTIL a2MHz_clk'EVENT AND a2MHz_clk = '1';

t1 <= t1 + 1;

END LOOP loop_t1;

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I can't imaging the RTL construction corresponding thise code.

First of all it would be better if you use sensitive list instead of wait and if ... then ...else construction to write your code. Because strings

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loop_t1 : WHILE wipe_on1 = '1' loop

WAIT UNTIL a2MHz_clk'EVENT AND a2MHz_clk = '1';

t1 <= t1 + 1;

END LOOP loop_t1;

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don't seems to me synthesisable.

P.S. Sorry for my english. It's not very good.

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Hi,

first of all you have a typo in the name of your entity ( photosensei ?). Next point is that

you could not use non-constant real values for synthesis. No synthesis tool is able to convert such value into logic. Real number could be used in simualtion only. I'm not a VHDL expert, but I think you have also a problem with the variable definitons of "seconds1, seconds2, secondst", because they are defined outside of the processes which are using it.

Kind regards

GPK

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Hello everyone, I think there's one more strange construction in the code:

I can't imaging the RTL construction corresponding thise code.

First of all it would be better if you use sensitive list instead of wait and if ... then ...else construction to write your code. Because strings

don't seems to me synthesisable.

P.S. Sorry for my english. It's not very good.

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Hi, thank you all for the reply.

GPK, I noticed that too when I tried to compile. It doesn't allow me to synthesize non-constant variables. The typo (photosensei) is due to my friend naming the code weirdly... I decided it change it when I post it here :D

I managed to solve the problem. I re-did the code and then my teammate said that I should use ieee.std_logic_arirth and ieee.std_logic_unsigned instead of std_numeric, because it was causing me problems for some reason. Instead of using variables I used integers and std_logic_vector only, because variables tend to be problematic (I think I read that somewhere in the forums).

Again, thanks for the suggestions. I appreciate it.

std_logic_unsigned and std_logic_arith are non-standard packages. numeric_std is a standard package. I would encourage you to use that if you can.

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Instead of using variables I used integers and std_logic_vector only, because variables tend to be problematic (I think I read that somewhere in the forums).

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As for this quote, you're getting it all mixed up. Variables can be anything, in the same way as signals. But they have different rules to signals and yes can cause problems if you dont use them correctly. But used correctly, they are very useful. You can only declare variables inside processes, functions or procedures.

And as starG has said, most of this code is unlikely to synthesise because you have more than one wait per process.

So many many problems with the code. I would recommend reading up on standard templates for digital logic and modifying your code to use them.

Hi Tricky,

I've written a new code, and it's cleaner and it's working now. That code was written by a friend of mine, who, like me, have limited knowledge of the code. But thanks for the suggestions, I will certainly keep that in mind.