Honored Contributor
Honored Contributorstd_logic_unsigned and std_logic_arith are non-standard packages. numeric_std is a standard package. I would encourage you to use that if you can.
--- Quote Start --- Instead of using variables I used integers and std_logic_vector only, because variables tend to be problematic (I think I read that somewhere in the forums). --- Quote End --- As for this quote, you're getting it all mixed up. Variables can be anything, in the same way as signals. But they have different rules to signals and yes can cause problems if you dont use them correctly. But used correctly, they are very useful. You can only declare variables inside processes, functions or procedures. And as starG has said, most of this code is unlikely to synthesise because you have more than one wait per process. So many many problems with the code. I would recommend reading up on standard templates for digital logic and modifying your code to use them.
