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arthurbg's avatar
arthurbg
Icon for New Contributor rankNew Contributor
25 days ago

EDA_MAINTAIN_DESIGN_HIERARCHY obsolete?

Hi Community,

I'm using Quartus Pro 25.1.1 and for simulation need to enable EDA_MAINTAIN_DESIGN_HIERARCHY during eda netlist writing. I wasn't able to find it somewhere in the settings and setting it via global assignment in qsf leads to this:

# Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation"
# Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation"

Does anyone know how to turn the hierarchy preservation on?

Thanks in advance!

 

Compilation
general
Simulation

2 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    22 days ago

    Unfortunately, EDA_MAINTAIN_DESIGN_HIERARCHY is not supported in Quartus Pro. It is only supported in Quartus Standard. 

    The only way to preserve any aspect of the hierarchy is to create design partition assignments at the required levels of hierarchy; however, this is not a feasible approach for preserving the entire hierarchy—only certain levels can be maintained.

    You can then use the quartus_eda command with the --partition argument to write out the netlist for the specific level.
    https://www.intel.com/content/www/us/en/docs/programmable/683432/25-3/partition-option.html

    Note also that if you create a simulation netlist for the top level then it will include the hierarchies with a design partition assignment.

    Regards,
    Richard Tan