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Altera_Forum's avatar
Altera_Forum
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13 years ago

Does VHDL has blocking and non blocking assignments?

I am a starter in VHDL (I only know Verilog before). I read some tutorial about VHDL. Now I am confused about assignment in VHDL. Does VHDL has blocking and non blocking assignments which are similar in Verilog?

In VHDL, there are two assignments "<=" and ":=". But it seems all signals are assigned through "<=", and variables are assigned by ":=". But in synthesised code, it seems always to use "<=" no matter combinational or sequential circuits. Does that mean in VHDL, there is not blocking and non-blocking assignements?

Hope someone who is familiar with VHDL can help me. Thanks very much!

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The real issue here is that signals can be used throughout a design and are usually registered, while variables can only be used within a VHDL process and take on immediate values. Often a variable is used to trigger another condition or state immediately within a process rather than waiting for the signal to be asserted on the next clock edge.

    Consider the case of a counter, declared with a record type, and used as a variable and then assigned as a signal (registered): 

    /*-------------------------------------------
           Count the number of samples
---------------------------------------------*/
counter.start <= START;
process(all) 
variable counterVal : integer range 0 to Nsamples;
begin
    if HRST then
        counterVal  := 0;
        counter.val   <= (others => '0');
        counter.done <= '0';
    elsif rising_edge(MCLK) then
        if load then
            counterVal := Nsamples-1;
            counter.done <= '0';
        elsif counter.start then
            if counter.val > 0  then
                 counterVal := counterVal - 1;
                counter.done <= '0';
            else
                counter.done <= '1';
            end if;
        end if;
    counter.val <= std_logic_vector(to_unsigned(counterVal,16));
    end if;
end process;
    where the record type is declared as: 

    type counterType is record
    start : std_logic;
    done  : std_logic;
    val   : integer range 0 to Nsamples-1;
end record;
signal counter : counterType;
    Conversely, consider the case of the same counter with signal type only. 

    /*-------------------------------------------
           Count the number of samples
---------------------------------------------*/
counter.start <= START;
process(all) begin
    if HRST then
        counter.val  <= 0;
        counter.done <= '0';
    elsif rising_edge(MCLK) then
        if load then
            counter.val <= Nsamples-1;
            counter.done <= '0';
        elsif counter.start then
            if counter.val > 0  then
                 counter.val <= counter.val - 1;
                counter.done <= '0';
            else
                counter.done <= '1';
            end if;
        end if;
    end if;
end process;
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    A VHDL variable assignment is working similarly to blocking procedural assignments in Verilog. They also work for synthesis. The main difference is the process local variable scope. "Global variables" exist in VHDL but are rarely supported for synthesis.

    Don't confuse Verilog blocking assignment with continuous assignments. The VHDL equivalent for the latter is a "<=" signal assignment in concurrent code.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    The real issue here is that signals can be used throughout a design and are usually registered, while variables can only be used within a VHDL process and take on immediate values. Often a variable is used to trigger another condition or state immediately within a process rather than waiting for the signal to be asserted on the next clock edge.

    But in following example:

    SIGNAL x1,x2,x3,f : STD_LOGIC;

    f<=(x1 AND x2) or x3;

    This code is actually same as in Verilog:

    assign f=(x1 && x2) || x3;

    and "<=" in VHDL (not registered) is actually same as "=" in Verilog, blocking assignment, right?

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    A VHDL variable assignment is working similarly to blocking procedural assignments in Verilog. They also work for synthesis. The main difference is the process local variable scope. "Global variables" exist in VHDL but are rarely supported for synthesis.

    Don't confuse Verilog blocking assignment with continuous assignments. The VHDL equivalent for the latter is a "<=" signal assignment in concurrent code.

    --- Quote End ---

    What is mean of "continuous assignments"? Do you mean "unblocking assignment" in Verilog?

    And since local variable can be used outside process, even for pure combinational model as following example in VHDL:

    SIGNAL x1,x2,x3,f : STD_LOGIC;

    f<=(x1 AND x2) or x3;

    We still use "<=" instead of ":=". But in this example, "<=" in VHDL should be same as "=" in Verilog, right?

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I did say "usually registered" as opposed to always registered. The code that you give below is an assignment, but not registered. In this case, the Verilog and VHDL are equal. -James

    --- Quote Start ---

    --- Quote Start ---

    The real issue here is that signals can be used throughout a design and are usually registered, while variables can only be used within a VHDL process and take on immediate values. Often a variable is used to trigger another condition or state immediately within a process rather than waiting for the signal to be asserted on the next clock edge.

    But in following example:

    SIGNAL x1,x2,x3,f : STD_LOGIC;

    f<=(x1 AND x2) or x3;

    This code is actually same as in Verilog:

    assign f=(x1 && x2) || x3;

    and "<=" in VHDL (not registered) is actually same as "=" in Verilog, blocking assignment, right?

    Thanks!

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    What is mean of "continuous assignments"? Do you mean "unblocking assignment" in Verilog?

    --- Quote End ---

    I thought you are familiar with Verilog terminology. Continuous assignments is the Verilog term for assignments outside procedures (always, function, task etc). 

    assign f=(x1 && x2) || x3;
    They are neither blocking nor non-blocking.

    VHDL is using <= for the same kind of assignments (assignments outside a process).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks very much, FvM. I am sorry, when I learned Verilog, I read some Chinese textbook, when you mentioned continuous assignment, I even didn't react what is that......