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Altera_Forum
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13 years ago

Does VHDL has blocking and non blocking assignments?

I am a starter in VHDL (I only know Verilog before). I read some tutorial about VHDL. Now I am confused about assignment in VHDL. Does VHDL has blocking and non blocking assignments which are similar...
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Altera_Forum
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13 years ago

A VHDL variable assignment is working similarly to blocking procedural assignments in Verilog. They also work for synthesis. The main difference is the process local variable scope. "Global variables" exist in VHDL but are rarely supported for synthesis.

Don't confuse Verilog blocking assignment with continuous assignments. The VHDL equivalent for the latter is a "<=" signal assignment in concurrent code.