Does VHDL has blocking and non blocking assignments?

I did say "usually registered" as opposed to always registered. The code that you give below is an assignment, but not registered. In this case, the Verilog and VHDL are equal. -James

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The real issue here is that signals can be used throughout a design and are usually registered, while variables can only be used within a VHDL process and take on immediate values. Often a variable is used to trigger another condition or state immediately within a process rather than waiting for the signal to be asserted on the next clock edge.

But in following example:

SIGNAL x1,x2,x3,f : STD_LOGIC;

f<=(x1 AND x2) or x3;

This code is actually same as in Verilog:

assign f=(x1 && x2) || x3;

and "<=" in VHDL (not registered) is actually same as "=" in Verilog, blocking assignment, right?

Thanks!

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