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A VHDL variable assignment is working similarly to blocking procedural assignments in Verilog. They also work for synthesis. The main difference is the process local variable scope. "Global variables" exist in VHDL but are rarely supported for synthesis.
Don't confuse Verilog blocking assignment with continuous assignments. The VHDL equivalent for the latter is a "<=" signal assignment in concurrent code.
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What is mean of "continuous assignments"? Do you mean "unblocking assignment" in Verilog?
And since local variable can be used outside process, even for pure combinational model as following example in VHDL:
SIGNAL x1,x2,x3,f : STD_LOGIC;
f<=(x1 AND x2) or x3;
We still use "<=" instead of ":=". But in this example, "<=" in VHDL should be same as "=" in Verilog, right?
Thanks!
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