Design facing fitter congestion need help
Hello Intel community,
Device used : 10AX057K4F35I3SG Family: Arria 10
I am facing the following and any help highly appreciated.
I have a huge design and I am getting routing congestion warning when build is completed
This is fitter report
Fitter Resource Usage Summary ;
------------------------------------------------------------+-------------------------+-------+
Resource ; Usage ; % ;
------------------------------------------------------------+-------------------------+-------+
Logic utilization (ALMs needed / total ALMs on device) ; 139,919 / 217,080 ; 64 % ;
ALMs needed [=A-B+C] ; 139,919 ; ;
[A] ALMs used in final placement [=a+b+c+d] ; 176,349 / 217,080 ; 81 % ;
[a] ALMs used for LUT logic and registers ; 57,016 ; ;
[b] ALMs used for LUT logic ; 44,742 ; ;
[c] ALMs used for registers ; 74,031 ; ;
[d] ALMs used for memory (up to half of total ALMs) ; 560 ; ;
[B] Estimate of ALMs recoverable by dense packing ; 37,808 / 217,080 ; 17 % ;
[C] Estimate of ALMs unavailable [=a+b+c+d] ; 1,378 / 217,080 ; < 1 % ;
[a] Due to location constrained logic ; 0 ; ;
[b] Due to LAB-wide signal conflicts ; 171 ; ;
[c] Due to LAB input limits ; 1,207 ; ;
[d] Due to virtual I/Os ; 0 ; ;
; ; ;
Difficulty packing design ; Low ; ;
; ; ;
Total LABs: partially or completely used ; 21,708 / 21,708 ; 100 % ;
-- Logic LABs ; 21,652 ; ;
-- Memory LABs (up to half of total LABs) ; 56 ; ;
; ; ;
Combinational ALUT usage for logic ; 177,275 ; ;
-- 7 input functions ; 677 ; ;
-- 6 input functions ; 35,960 ; ;
-- 5 input functions ; 18,012 ; ;
-- 4 input functions ; 15,260 ; ;
-- <=3 input functions ; 107,366 ; ;
Memory ALUT usage ; 1,008 ; ;
-- 64-address deep ; 0 ; ;
-- 32-address deep ; 1,008 ; ;
; ; ;
; ; ;
Dedicated logic registers ; 325,662 ; ;
-- By type: ; ; ;
-- Primary logic registers ; 262,093 / 434,160 ; 60 % ;
-- Secondary logic registers ; 63,569 / 434,160 ; 15 % ;
-- By function: ; ; ;
-- Design implementation registers ; 318,507 ; ;
-- Routing optimization registers ; 7,155 ; ;
Please guide me if there are any optimization technique in the tool.
The design is almost optimised and very slim possibility of reducing the resources.
Thank you
Regards
Pavan Hegde