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pavanhegde's avatar
pavanhegde
Icon for New Contributor rankNew Contributor
4 years ago

Design facing fitter congestion need help

Hello Intel community, Device used : 10AX057K4F35I3SG Family: Arria 10 I am facing the following and any help highly appreciated. I have a huge design and I am getting routing congestion warning...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Pavan,

We did not receive any response to the previous question/reply/answer provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

  • pavanhegde's avatar
    pavanhegde
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello @Nurina

    Sorry for the delay.
    Yes the LAB usage was reduced to 97% and we have reduced ALM (optmised the code)

    But the results of the FPGA build are not consistent

    Sometimes the build will take 100%
    Strange thing is it is not showing any routing congestion even LAB's utilization is 100%

    I know that 100% LAB is not good but since there is no warning or error it is confusing

    How about your opinion?

    Thank you
    Regards
    Pavan Hegde