New Contributor
Regular ContributorHi Pavan,
The congestion might be caused by the place and route, this problem arises a lot in Arria 10 devices. Maybe you can set a LogicLock region to solve this.
You can refer to this document on Design Optimization Floorplan: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-optimization.pdf#page=121
Regards,
Nurina
New ContributorHello @Nurina
I am new to Intel design flow and LogicLock region technique is little difficult for me
However I tried different method.
I changed few settings in Analysis and synthesis , fitter settings.
|
Earlier option:-1 Unlimited New option: 21708 (Maximum Number of LABs) |
| Earlier option : balanced | New option: Area (Optmization technique) | |||||||
| Earlier option: 1.0 | New Option: 2.0 (Placement Effort Multiplier) | |||||||
The utilization of LABs is 99% now ( almost 300 LABs reduced)
Do you know what is crtical limit for the usage of LABs?
Please suggest me
Thank you
Regards
Pavan
