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pavanhegde's avatar
pavanhegde
Icon for New Contributor rankNew Contributor
5 years ago

Design facing fitter congestion need help

Hello Intel community, Device used : 10AX057K4F35I3SG Family: Arria 10 I am facing the following and any help highly appreciated. I have a huge design and I am getting routing congestion warning...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Pavan,


In my opinion it's best to use up around 80-90% resources so you can use the free resources for debugging like SignalTap. If you don't plan on using SignalTap then I think 97% is fine.


With regards to the inconsistent resource usage, this is expected because you didn't set logic lock region, so the fitter will place & route your design differently at each compilation, using different amount of LAB.


Regards,

Nurina