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Sruthy's avatar
Sruthy
Icon for New Contributor rankNew Contributor
1 year ago

Design Compilation Error in quartus prime

Hi,

I am beginner to quartus prime. I am facing an error as shown below:

ID:21358 Verilog HDL error at <location>: '<string>' is not a port

but the port is already declared as input

Error(21358): Verilog HDL error at d_ip_i3c_mipi_syn.v(398): 'scan_no_rst_alt' is not a port

input [3:0] scan_no_rst_alt

how to resolve this?

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Without seeing more code, there's really no way to figure out what is going on.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Without looking at the code, it is hard to debug what might cause the error.

    Please share the design file or project (Project > Archive Project) that could duplicate the error.


    Regards,

    Richard Tan


  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

    If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

    The community users will be able to help you on your follow-up questions.

    Thank you for reaching out to us!

    Best Regards,

    Richard Tan