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Altera_Forum
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10 years ago

Delaying signal in a specific wire using TimeQuest

Hello,

I'm getting very frustrated after spending some time reading the TimeQuest booklet and watching the training videos since I'm unable to understand haw one can describe the following problem using constraints.

I have the following schematic file:

http://www.alteraforum.com/forum/attachment.php?attachmentid=11035&stc=1

I have a clock signal that feeds three different modules. However, due to computation delays in module LCG, I need to also delay the clock signal applied to the "registo2" memory block. If the computation time delay is, for example, 2 ns and I want to delay the memory clock signal by 3 ns how can I describe this in Time Quest? Any help will be very appreciated. For now I'm considering using a PLL for create a second clock signal with phase delay regarding the main clock. However I think this can be circumvent by proper timing definitions. However I don't know how...

Regards.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    This is impossible, and not how timequest works. Because your design is synchronous, you shouldnt care about the delay through LCG, because it will appear some clocks after starting. The whole point of having a synchronous design means you dont care about path delays. You just care that the paths are short enough so the data arrives before the next clock edge (and the fitter/timequest do this for you). You should never ever delay a clock you fix the logic.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Dear Tricky,

    Can you please provide more information regarding your statement "you shouldnt care about the delay through LCG, because it will appear some clocks after starting"?

    In this particular case the register address, provided by the counter, and the data, provided by the LCG module, must be stable prior to the register rising edge clock signal. Have you any tip for how to do that? Should I change the schematic structure?

    Regards.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    They will be stable assuming that the design passed timing. Thats the point of timing analysis.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    jpcoelho,

    I'm not sure what to tell you, other than what Tricky has already pointed out; You have a design problem, not a timing problem.

    You need to take a step back and understand the overall nature of synchronous logic design. You'll see that its great virtue is that most timing problems "take care of themselves".