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Altera_Forum
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11 years ago

Delaying signal in a specific wire using TimeQuest

Hello, I'm getting very frustrated after spending some time reading the TimeQuest booklet and watching the training videos since I'm unable to understand haw one can describe the following prob...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

jpcoelho,

I'm not sure what to tell you, other than what Tricky has already pointed out; You have a design problem, not a timing problem.

You need to take a step back and understand the overall nature of synchronous logic design. You'll see that its great virtue is that most timing problems "take care of themselves".