Delaying signal in a specific wire using TimeQuest

This is impossible, and not how timequest works. Because your design is synchronous, you shouldnt care about the delay through LCG, because it will appear some clocks after starting. The whole point of having a synchronous design means you dont care about path delays. You just care that the paths are short enough so the data arrives before the next clock edge (and the fitter/timequest do this for you). You should never ever delay a clock you fix the logic.