Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Delaying signal in a specific wire using TimeQuest

Hello, I'm getting very frustrated after spending some time reading the TimeQuest booklet and watching the training videos since I'm unable to understand haw one can describe the following prob...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Dear Tricky,

Can you please provide more information regarding your statement "you shouldnt care about the delay through LCG, because it will appear some clocks after starting"?

In this particular case the register address, provided by the counter, and the data, provided by the LCG module, must be stable prior to the register rising edge clock signal. Have you any tip for how to do that? Should I change the schematic structure?

Regards.