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Altera_Forum
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16 years ago

Debugging using the Quartus simulator?

Hi,

I have designed a simple block to be programmed onto FPGA.

Currently there is a bug which I am trying to find - I am using the quartus simulator and would like to know if annybody knows how to setup the simulator so that I can view internal signal values after the simulation has completed. Can find in manual.

So far I can only get it to report the values of the top level pins which is not helping me.

Thanks in advance!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi,

    I have designed a simple block to be programmed onto FPGA.

    Currently there is a bug which I am trying to find - I am using the quartus simulator and would like to know if annybody knows how to setup the simulator so that I can view internal signal values after the simulation has completed. Can find in manual.

    So far I can only get it to report the values of the top level pins which is not helping me.

    Thanks in advance!

    --- Quote End ---

    Hi,

    you have to define the signals in your <>.vwf.

    Open the file and:

    double-click into the "Name" column

    A new window pops-up "Insert Node or Bus"

    Click on "Node Finder" and choose your signals

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi GPK,

    what you descibe is pritty much what I was doing but am getting the following warnings when I start the simulation.

    Info: Using vector source file "vhdl/peripherals.vwf"

    Warning: Can't find node "tst_peripherals_trans:uut|counter[3]" for functional simulation. Ignored vector source file node.

    this internal node is a register so bit surpried that it cannot be found - any ideas?

    thanks,

    John.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi GPK,

    what you descibe is pritty much what I was doing but am getting the following warnings when I start the simulation.

    Info: Using vector source file "vhdl/peripherals.vwf"

    Warning: Can't find node "tst_peripherals_trans:uut|counter[3]" for functional simulation. Ignored vector source file node.

    this internal node is a register so bit surpried that it cannot be found - any ideas?

    thanks,

    John.

    --- Quote End ---

    Hi John,

    did you choose "post-synthesis" Nodes ?

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi GPK,

    I choose pre synthesis nodes as I had not yet gone through the synthesis flow as want to verify my design first. Is this wrong?

    Thanks,

    John.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi GPK,

    I choose pre synthesis nodes as I had not yet gone through the synthesis flow as want to verify my design first. Is this wrong?

    Thanks,

    John.

    --- Quote End ---

    Hi John,

    it seems that some optimizations takes place by generating the functional netlist. Your warning indicates that the counter bit is obsolet in your design. It is at least a misleading behaviour of the simulator.

    Kind regards

    GPK