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Altera_Forum
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16 years ago

Debugging using the Quartus simulator?

Hi, I have designed a simple block to be programmed onto FPGA. Currently there is a bug which I am trying to find - I am using the quartus simulator and would like to know if annybody kn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi GPK,

I choose pre synthesis nodes as I had not yet gone through the synthesis flow as want to verify my design first. Is this wrong?

Thanks,

John.

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Hi John,

it seems that some optimizations takes place by generating the functional netlist. Your warning indicates that the counter bit is obsolet in your design. It is at least a misleading behaviour of the simulator.

Kind regards

GPK