New ContributorI'm using Quartus prime 20.1.1.
When using Arria 10 to capture data from an ADC with a DDR type data output that can sample at 160MHz, when I used DDRIO IP, the DDRIO circuit was not placed in the IOC. Please tell me the cause and countermeasure.
Regular ContributorHi,
Thank you for reaching out FPGA community.
For your issue, I need to understand more about your design,
Can you share your top-level diagram of the design?
I also need clarification on the OIC. Can you elaborate more on that?
Regards,
Aqid
New ContributorThe figure below shows the data input section from the ADC.
The data and clock from the ADC are received via LVDS.The figure below shows one bit of "ad_d0_[6..0]" shown in the figure above when viewed using a chip planner.The above circuit is not placed in the "DDIO IN" block at the bottom right of the chip planner.
How can I place it in the "DDIO IN" block at the bottom right of the chip planner?best regards.
New ContributorI solved the problem.
I confirmed that the IOC has a DDR element other than the DDRIN block.Regular ContributorHello,
I'm glad the issue you are facing is solve. May I know if you need any other support on this?
Regards,
Aqid
New ContributorDear Aqid.
Thank you for your support.
There is nothing else.Regular ContributorThank you for the confirmation. I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response.
p/s: If you feel the support is excellence, feel free to rate "Very Satisfied" once you get the evaluation survey. I appreciate your kindness.
