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sun_tak's avatar
sun_tak
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2 years ago

DDRIO IP block is not placed in IOC.

I'm using Quartus prime 20.1.1. When using Arria 10 to capture data from an ADC with a DDR type data output that can sample at 160MHz, when I used DDRIO IP, the DDRIO circuit was not placed in the I...
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sun_tak's avatar
sun_tak
Icon for New Contributor rankNew Contributor
2 years ago
The figure below shows the data input section from the ADC.
The data and clock from the ADC are received via LVDS.

The figure below shows one bit of "ad_d0_[6..0]" shown in the figure above when viewed using a chip planner.

The above circuit is not placed in the "DDIO IN" block at the bottom right of the chip planner.
How can I place it in the "DDIO IN" block at the bottom right of the chip planner?
best regards.