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sun_tak's avatar
sun_tak
Icon for New Contributor rankNew Contributor
2 years ago

DDRIO IP block is not placed in IOC.

I'm using Quartus prime 20.1.1. When using Arria 10 to capture data from an ADC with a DDR type data output that can sample at 160MHz, when I used DDRIO IP, the DDRIO circuit was not placed in the I...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Thank you for reaching out FPGA community.


For your issue, I need to understand more about your design,

Can you share your top-level diagram of the design?

I also need clarification on the OIC. Can you elaborate more on that?


Regards,

Aqid