Forum Discussion
Occasional Contributordcfifo problem
In our project, we instantiate the parameterizable DCFIFO primitive provided by Altera. The design passes simulation verification without issues; however, mismatches occur between written and read data from the DCFIFO by signalTAP during board-level testing , which consequently causes driver loading failures.
fpga device：agilex7 with quartus pro25.3
dcfifo wr_clk: 450M
dcfifo rd_clk: 416M
the instantiate example:
is there better suggestion?
3 Replies
sstrellSuper Contributor
This could also be a timing issue. Is your design closing timing?
BCuzeI'm curious about how you test the discrepancy.
From which clock does Signaltap run ? IMO, you should have two STPs, one on each clock.Did you try pushing PRBS data and check what comes out ? Easier than STP IMO.
ShengN_alteraHi,
Possible provide simulation waveform and signal tap waveform for taking a look? Or possible provide design for taking a look?
