CycloneVsoc dev kit UART read from FPGA/HPS

Question

Hi,My hardware is Cyclone V soc Dev kit with software of newest version of GHRD.I encountered several questions on handling the UART. 1. According to the GHRD QSYS HPS Mux Table:UART RX/TX was sent to CAN RX/TXCAN RX/TX was sent to UART RX/TXIs that mean my set to UART port (software wide) is linked to CAN(hardware wide,J35 CAN )and my CAN port(software) is linked to UART (J8 with RX/TX option)?If is that so, then auto_semihosting is always sending through CAN (software) with UART(J8 port)?2. FPGA reading/sending through UARTHow to let FPGA read/write through HPS UART? In the HPS design tab I can set the UART to FPGA, and get the export port, but how to use that port?Another question would be : can hps use UART at the same time? Like when I was debugging through arm ds and then transfer the data to FPGA and let FPGA send the data to my host.3. Let's say the answer of the 2nd question is NO, HPS and FPGA cant communicate with UART at the same time, then how do I manage the CAN port. I mean what's the data width of CAN port,where can I find the information etc.4.How to send data to the on-chip-ram from HPS and let FPGA receive data from the OCRAM.According to the GHRD:There is an 65536 bit on chip ram on FPGA side.Is that the same ram used in HPS example Makefile(make memory = ocr)?As I know the on-chip memory is 0xC000_0000 + RAM offset, but the OCR is 0xFFFF0000 right?5. How to instore the codes in the ROM?Now I'm debugging the bare metal projects with ARM DS, but I must download/boot the board every time, is there some methods to solve this problem?That's it.Looking forward to ur replyReguardsAlex

tehjingy_altera · Answer

Hi Alex1)That is the Mux table.The mux table shows the possible pins that the pins could be switched to.In the GHRD the UART0 (Set 2) and CAN0 (Set 0) was selected.From the MUX table they are different pins.2)There is a dedicated UART from the HPS.I don't quite understand what you are trying to achieve here.You could add a soft IP in the FPGA fabric and connect it to the HPS UART.4)Could you point me to the make file that you are referring to?5)There is a way you could place your baremetal code in teh QSPI flash and with the uboot. launch the baremetal application.You could refer to the word document attached.RegardsJingyang, Teh

calex · Answer

2. What I want to achieve is that I want to use HPS calculate and send the data to the on-chip ram IP and let FPGA read/write and then send them to the host through UART/CAN. Since I need to use UART(J8) as semihosting I can only use CAN.

4. On the baremetal example, each one of them will have a choice of MEMORY ?= DDR/OCR. If I choose OCR the entry point would be 0xFFFF0000 right?

tehjingy_altera · Answer

Hi AlexFor transfering of data between the HPS and FPGA fabric. You could use a DMA to transfer data in between.You could refer to the example here:https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.htmlYes, the entry point for on-chip ram is 0xFFFF0000.RegardsJingyang, Teh

tehjingy_altera · Answer

Hi Do you have any new updates for this case?RegardsJingyang, Teh

calex · Answer

We bought a module to set the SPIM as the Uart, I now finished the host program to read that.

And the FPGA side I loan the HPS IO to the FPGA and they communicated with each other successfully.

But SOC(HPS) side there are two issues:

1. how to let HPS send the data to a RAM(an FPGA IP along with the GHRD).

2. how to let uart receive the data from that IP.

Reguards

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CycloneVsoc dev kit UART read from FPGA/HPS

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