Contributor
Regular ContributorHi Alex
1)
That is the Mux table.
The mux table shows the possible pins that the pins could be switched to.
In the GHRD the UART0 (Set 2) and CAN0 (Set 0) was selected.
From the MUX table they are different pins.
2)
There is a dedicated UART from the HPS.
I don't quite understand what you are trying to achieve here.
You could add a soft IP in the FPGA fabric and connect it to the HPS UART.
4)
Could you point me to the make file that you are referring to?
5)
There is a way you could place your baremetal code in teh QSPI flash and with the uboot. launch the baremetal application.
You could refer to the word document attached.
Regards
Jingyang, Teh
Contributor2. What I want to achieve is that I want to use HPS calculate and send the data to the on-chip ram IP and let FPGA read/write and then send them to the host through UART/CAN. Since I need to use UART(J8) as semihosting I can only use CAN.
4. On the baremetal example, each one of them will have a choice of MEMORY ?= DDR/OCR. If I choose OCR the entry point would be 0xFFFF0000 right?
