Alberto_G
New Contributor
New ContributorCyclone V Gate-Level simulation
Hi all, I'm trying to perform a gate-level functional simulation using a FPGA from the Cyclone V family (I know that gate-level + timing simulations are not suported for this type of FPGA), after co...
Hi,
Make sure you're following the steps shown in this video https://www.youtube.com/watch?v=HFWd7QPibMY&t=476s
Make sure also there's no problem with the testbench.
Attached a minimal sample design on gate-level simulation and respective script.
Thanks,
Regards,
Sheng
