Customize pattern generator created in Qsys

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I have a question about the avalon_to_st_ram. In my case I want to initialize the RAM with a .mif file. In this case I think I don't need a FIFO, right? because I want to create a .mif fixed that it will be my pattern and I want that this .mif repeats every time. Or should my xcvr_low_latency_phy read from a fifo instead of the RAM directly? if I initialize my RAM, It is not necessary a dual-clock, isn't it?

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Sure, if you want a fixed pattern, and that pattern can fit in on-chip RAM, then you can use a single-ported RAM initialized from a .mif file and use a single clock domain.

However, if you've ever had to debug a system, you'll realize that one pattern is generally not enough :)

For example, I only have a 1GHz scope, so when looking at 5Gbps and 10Gbps lanes, I load a RAM pattern that repeats at a much lower frequency, eg., a square-wave.

Your system design should always include an option for debug access, eg., a JTAG connector, so having an option to load the RAM does not "cost" much.

Cheers,

Dave

Hello again,

Finally, I have decided to make another design. This consists in a qsys system with a clock system, a ref. clock, a jtag to avalon master bridge and 3 external slave interfaces ( 1 exports avalon signals to interface with Low_Latency PHY core, another exports to the Reconfiguration Controller and the last exports to a RAM-2ports). All of that modules have been created using Megawizard. I have started with a RAM-2port of 32 words x 8 bit with a single clock and I have initialized with a .mif file. The content of this .mif file is what i want to get in the output of one of the channels of the Stratix V transceivers (transmitting to 2,5 Gbps) i.e. I would like the content of this file that consists in binary sequence is continually repeated. This design compiles and load in the board without any problem, but when I test the signal in the DSO it seems I am transmitting just the clock signal, that means that my protocol low_latency is not reading from my dual_port RAM. Any idea how could I fix this problem?

Thank you!

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Any idea how could I fix this problem?

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You should first simulate the design :)

Cheers,

Dave

Thanks Dave, Could you give some advices how can I simulate? I am really new in simulations, actually I am new working with FPGAs :).

Which simulation tool would be the best for simulate this design? Modelsim? Should I simulate every block separately? Should I simulate only the memory?Do you know any manual for beginners?

Thanks

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Could you give some advices how can I simulate?

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Sure, go through this tutorial, it simulates most of what you are using;

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

Note that Altera have changed the format of the Modelsim setup_sim.tcl script they create for simulating their IP in the latest version of the tools, so use exactly the version of Quartus I use in the tutorial. Once you have the tutorial working, you can move to the newer version of the tools and figure out the differences. I'll update the tutorial for version 12.1sp1 and 13.0 when I get time, but that is not now :)

Cheers,

Dave