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I have a question about the avalon_to_st_ram. In my case I want to initialize the RAM with a .mif file. In this case I think I don't need a FIFO, right? because I want to create a .mif fixed that it will be my pattern and I want that this .mif repeats every time. Or should my xcvr_low_latency_phy read from a fifo instead of the RAM directly? if I initialize my RAM, It is not necessary a dual-clock, isn't it?
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Sure, if you want a fixed pattern, and that pattern can fit in on-chip RAM, then you can use a single-ported RAM initialized from a .mif file and use a single clock domain.
However, if you've ever had to debug a system, you'll realize that one pattern is generally not enough :)
For example, I only have a 1GHz scope, so when looking at 5Gbps and 10Gbps lanes, I load a RAM pattern that repeats at a much lower frequency, eg., a square-wave.
Your system design should always include an option for debug access, eg., a JTAG connector, so having an option to load the RAM does not "cost" much.
Cheers,
Dave
Honored Contributor
