Altera_ForumHonored Contributor13 years agoCustomize pattern generator created in Qsys I did a design for Stratix V GX FPGA in order to transmit 3 independent channels. This design was created using qsys, also the pattern generator and the pattern_checker were created in qsys. Now I ne...Show More
Altera_ForumHonored Contributor13 years ago --- Quote Start --- Any idea how could I fix this problem? --- Quote End --- You should first simulate the design :) Cheers, Dave
Recent DiscussionsHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorConnection bit order between hierarchyCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: