Customize pattern generator created in Qsys

Hello again,

Finally, I have decided to make another design. This consists in a qsys system with a clock system, a ref. clock, a jtag to avalon master bridge and 3 external slave interfaces ( 1 exports avalon signals to interface with Low_Latency PHY core, another exports to the Reconfiguration Controller and the last exports to a RAM-2ports). All of that modules have been created using Megawizard. I have started with a RAM-2port of 32 words x 8 bit with a single clock and I have initialized with a .mif file. The content of this .mif file is what i want to get in the output of one of the channels of the Stratix V transceivers (transmitting to 2,5 Gbps) i.e. I would like the content of this file that consists in binary sequence is continually repeated. This design compiles and load in the board without any problem, but when I test the signal in the DSO it seems I am transmitting just the clock signal, that means that my protocol low_latency is not reading from my dual_port RAM. Any idea how could I fix this problem?

Thank you!