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Altera_Forum
Honored Contributor
Honored ContributorCritical warning about asynchronous clock domains from same PLL
Hey there,
I have an FPGA design where a part is running at 150MHz and one part is running with 75MHz (both sourced from the same PLL). So, IMHO the clocks should be synchronous. Of course I need to bring data from one clock domain to another clock domain and I am using a 2FF synchronizer. I already did this also in other designs (eg. MAX10) and AFAIR it worked flawlessly. Now I have a Cyclone IV-FPGA and during synthesis I get a critical warning D101: Data bits are not synchronized when transferred between asynchronous clock domains... My SDC-file has the following entries:set_time_format -unit ns -decimal_places 3
create_clock -name {clk_ext} -period 50.000 -waveform { 0.000 25.000 }
derive_pll_clocks
derive_clock_uncertainty 15 Replies
Altera_ForumI don't know where the *pll1* is coming from, but in the compilation report under Flow Summary Quartus states that 1/4 (25%) of the PLLs are used. I also don't have any command about unrelated clocks in the sdc. You can also have a look at my other post where I did a write_sdc -expand (Result: https://pastebin.com/dhefpn2e)
- Altera_Forum--- Quote Start --- I don't know where the *pll1* is coming from, but in the compilation report under Flow Summary Quartus states that 1/4 (25%) of the PLLs are used. I also don't have any command about unrelated clocks in the sdc. You can also have a look at my other post where I did a write_sdc -expand (Result: https://pastebin.com/dhefpn2e) --- Quote End --- It is strange that the tool reports unrelated clocks. Any reason why duty cycle is 50/1 on each clock??
- Altera_Forum--- Quote Start --- It is strange that the tool reports unrelated clocks. Any reason why duty cycle is 50/1 on each clock?? --- Quote End --- I don't know, I think this happens due to the write_sdc -expand command. My original SDC-file does not contain these lines (see my first post). But looking in the documentation of SDC Commands (https://www.altera.com/en_us/pdfs/literature/manual/mnl_sdctmq.pdf) at page 2-8: duty_cycle is given in percent, so I think this value corresponds to 50% duty cycle. I think this is OK. Looking in the compilation report states also that the duty cycle is 50.00 for each PLL generated clock. IMHO this is not a problem.
- Altera_Forum
It is clear that tool regarded clk[0] @150Mhz & clk[1] @75MHz as asynchronous for some reason. It could be they are not in phase or pll mode may be dictating that...
So regard it as asynchronous and then you have to cross domains based on double synchronisers. But you did say you done that, or have you done that properly as the reported paths deny it. - Altera_Forum
As far as I see I do not have any strange settings in the PLL. I will ignore this warnings and I will see, if my design fails sometime.
Thank you for your ideas and hints :)
