Firstly, it would be more helpful if you could explain what you mean by a CSR, as typing the term into Google + state machine yields results where the term is defined as a Certificate Signing Request and as that has to do with SSL certificates I highly doubt that is what you intended. The interrupt is an interesting idea. Basically, I am referring to the hardware-defined custom IP in Platform Designer. There's a lot of hardware out there, including as peripherals. Some can get away with not being defined as FSMs, but others cannot. For example, a peripheral being defined as a Custom IP in Verilog to perform let's say for argument's sake, I'm having a hard time thinking of something that isn't what I'm working on directly so please forgive me, but for example's sake let's say it performs division. As a hardware defined module, it does this maybe slightly faster and that's why we want to use it instead.of software. Now, let's say to do that our hardware divider, as written in Verilog, works hunky dory when run on an FPGA but takes multiple states to complete the operation. However, looking at the offical documentation (link:
https://cdrdv2-public.intel.com/667068/mnl_avalon_spec-683091-667068.pdf&ved=2ahUKEwjA8I-f7pqEAxVXGDQIHfAmA4sQFnoECBUQAQ&usg=AOvVaw2pQFtXw-YNlJe_-IN6QHxI) I'm struggling to wrap my head around taking such a peripheral that takes multiple clock cycles to complete its task (and thus have the correct output in the output register) and changing it into a standardized interface to work as a Custom IP module with Nios II. Hope that clairifies!
New Contributor
