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road_runner's avatar
road_runner
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2 years ago

Creating Finite State Machine Based Custom IP for Nios II

Hello, I've created a simple if-then type decoder as custom IP for Nios before, however, all it needed to do was look at an input number, go to the right if-then statement to select the correct outp...
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sstrell's avatar
sstrell
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2 years ago

Huh?

This is a very confusing description.

You want to create a state machine, yet you are using a Nios processor so you could write software code to do whatever you need.

You need the state machine to go through all states and get to a particular state. OK, so what are the requirements for the state transitions? Are there inputs that control the state transitions? How do you get to this final state that you need it to get to?

Then I think you are saying that when you get to this final magic state, how do you let the Nios processor know that this has happened? You could create a CSR as part of the state machine (or a separate component) that sets a bit the processor could read over an Avalon interface. Or better yet, the state machine could send an interrupt to the processor directly instead of having to build a register.

I have no idea if any of this is helpful.

road_runner's avatar
road_runner
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2 years ago
Firstly, it would be more helpful if you could explain what you mean by a CSR, as typing the term into Google + state machine yields results where the term is defined as a Certificate Signing Request and as that has to do with SSL certificates I highly doubt that is what you intended. The interrupt is an interesting idea. Basically, I am referring to the hardware-defined custom IP in Platform Designer. There's a lot of hardware out there, including as peripherals. Some can get away with not being defined as FSMs, but others cannot. For example, a peripheral being defined as a Custom IP in Verilog to perform let's say for argument's sake, I'm having a hard time thinking of something that isn't what I'm working on directly so please forgive me, but for example's sake let's say it performs division. As a hardware defined module, it does this maybe slightly faster and that's why we want to use it instead.of software. Now, let's say to do that our hardware divider, as written in Verilog, works hunky dory when run on an FPGA but takes multiple states to complete the operation. However, looking at the offical documentation (link: https://cdrdv2-public.intel.com/667068/mnl_avalon_spec-683091-667068.pdf&ved=2ahUKEwjA8I-f7pqEAxVXGDQIHfAmA4sQFnoECBUQAQ&usg=AOvVaw2pQFtXw-YNlJe_-IN6QHxI) I'm struggling to wrap my head around taking such a peripheral that takes multiple clock cycles to complete its task (and thus have the correct output in the output register) and changing it into a standardized interface to work as a Custom IP module with Nios II. Hope that clairifies!
  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    CSR= control and status registers, basic access and data passing for any memory-mapped interface. But what you’re now talking about is a custom instruction for Nios. Look up how to create custom instructions and tie them in to the processor’s instruction set to hardware accelerate a function like the division you mention.