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Altera_Forum
Honored Contributor
Honored Contributorcontinuous averaging using VHDL
I have a question related to VHDL programming. I want to calculate the continuous average. My example code is:
process (clk, reset)
begin
if (reset = '1') then
state<=idle;
out-val=0;
elsif(rising_edge(clk)) then
case state is
when idle =>
if req='1' then
state= out-1;
end if;
when out-1 =>
if done='1' then
out-val<=data-in (11 downto 0)
state <= done-st;
endif;
when done-st =>
ack <='1';
state <= idle;
when others =>
state <= idle;
end case;
end if;
end process;
90 Replies
Altera_ForumI updated the previous post. I am posting it again.
@kaz Yes I mean to concatenate them. I have two ADCs. Each ADC has two 12 bit inputs that captures the value. One ADC is for current measurement and the other for voltage measurement. The voltage measurement ADC is fine and I don't need filter for that. I need the filter for current measurement ADC. I concatenate the four outputs (two from first ADC and two outputs from second ADC) into 48 bits. I am doing the 'and' or concatenate on the top level. Then I am passing the concatenated value to the GUI via USB interface. These 48 bits value represents the Current and voltage.- Altera_Forum
"I have two ADCs, each ADC has 12 bit inputs (you mean outputs)"
"two outputs from first ADC..."??? what is the sample width of your current ADC? is it 12 bits or 24 bits? - Altera_Forum--- Quote Start --- "I have two ADCs, each ADC has 12 bit inputs (you mean outputs)" "two outputs from first ADC..."??? what is the sample width of your current ADC? is it 12 bits or 24 bits? --- Quote End --- Yes I mean two 12 bit outputs Its 12 bits.
- Altera_Forum
is it possible to know the ADC device you are using just to make up my mind why it is 12 bits and 24 bits.
- Altera_Forum--- Quote Start --- is it possible to know the ADC device you are using just to make up my mind why it is 12 bits and 24 bits. --- Quote End --- Yes. I am using ADC122S021
- Altera_Forum
This device has figures for Fsclk & Fs separately.
I understand that min Fs is 50Ksps and max Fs is 200Ksps. The Fsclk has then to be fast enough for 12 bits (in fact 16 times as Fs) i.e. Fsclk(min) = .8MHz and 3.2MHz(max). Yet you are using Fsclk of 15KHz i.e. Fs = 15KHz/16 = .9KHz appart from violating device spec. Am I right? - Altera_Forum--- Quote Start --- This device has figures for Fsclk & Fs separately. I understand that min Fs is 50Ksps and max Fs is 200Ksps. The Fsclk has then to be fast enough for 12 bits (in fact 16 times as Fs) i.e. Fsclk(min) = .8MHz and 3.2MHz(max). Yet you are using Fsclk of 15KHz i.e. Fs = 15KHz/16 = .9KHz appart from violating device spec. Am I right? --- Quote End --- The FSclk is 312KHz which means Fs= 312/16=19.5 KHz
- Altera_Forum--- Quote Start --- The FSclk is 312KHz which means Fs= 312/16=19.5 KHz --- Quote End --- OK assuming 19.5Ksps is not violating spec then I don't see why you shouldn't get the mean quickly. Your accumulator will settle after 256 samples i.e. within msec(you have 19.5Ksps) You better check in signaltap or simulation what is causing this delay. It should be easy as you can check sum and avg all the way through. your accummulator bitwidth of 20 bits is just right (12 bits + 8bits = 20bits) so there is no overflow.
- Altera_Forum--- Quote Start --- OK assuming 19.5Ksps is not violating spec then I don't see why you shouldn't get the mean quickly. Your accumulator will settle after 256 samples i.e. within msec(you have 19.5Ksps) You better check in signaltap or simulation what is causing this delay. It should be easy as you can check sum and avg all the way through. your accummulator bitwidth of 20 bits is just right (12 bits + 8bits = 20bits) so there is no overflow. --- Quote End --- Ok. I will check in the simulation what is causing the delay. But one thing I am confused is about those slowly incrementing values. I don't know why I see like 4mA, 8 mA, 16mA,,..... finally stable value of 100mA. I don't know why it is not just showing me 100mA directly.
- Altera_Forum--- Quote Start --- Ok. I will check in the simulation what is causing the delay. But one thing I am confused is about those slowly incrementing values. I don't know why I see like 4mA, 8 mA, 16mA,,..... finally stable value of 100mA. I don't know why it is not just showing me 100mA directly. --- Quote End --- If your adc data is a constant (or so) then your accumulator (plus division by 256) will build up from zero gradually then settle at the constant value when sample 255 arrives from stage 255 i.e. it should be within msec not second. during this initial time there is subtraction from zero and so the summed up total divided by 2^8 will be less than constant until all 256 samples are added and divided by 2^8 to equal the constant. Thereafter any new sample arrival is added but last one subtracted leading to same constant.
