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Altera_Forum's avatar
Altera_Forum
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13 years ago

continuous averaging using VHDL

I have a question related to VHDL programming. I want to calculate the continuous average. My example code is: process (clk, reset) begin if (reset = '1') then state<=idle; out-v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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The FSclk is 312KHz which means Fs= 312/16=19.5 KHz

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OK assuming 19.5Ksps is not violating spec then I don't see why you shouldn't get the mean quickly. Your accumulator will settle after 256 samples i.e. within msec(you have 19.5Ksps)

You better check in signaltap or simulation what is causing this delay. It should be easy as you can check sum and avg all the way through.

your accummulator bitwidth of 20 bits is just right (12 bits + 8bits = 20bits) so there is no overflow.