Constraints on DDR signals

It would be helpful if you could teach me how to give constraints to the DDR signal from the ADC.

The conditions are as follows.

　CLK　: 200MHz

　DATA resolution: 14bit

　Signal level: LVDS

　CLK-DATA skew:

　　　min　1ns

　　　max　1.6ns

(Rise/fall of CLK at the center of DATA)

The source synchronous system is used, and the clock and data are directly connected to the FPGA.

Also, data and clock are wired with equal length on the board.

In the case of DDR, I am aware that constraints are set for both rising and falling edges, so the constraints are described as follows.

--From here

create_clock -name DCLK -period 5 [get_ports {CLK}]

set_input_delay -clock { CLK } -max 1.5 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[ 9] DATA[10] DATA[11] DATA[12] DATA[13]}]

set_input_delay -clock { CLK } -clock_fall -max -add_delay 1.5 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[ 8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13]}]

set_input_delay -clock { CLK } -min 0.9 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[ 9] DATA[10] DATA[11] DATA[12] DATA[13]}]

set_input_delay -clock { CLK } -clock_fall -add_delay 0.9 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13]}]

--to this point

It seems that the data is being received normally, but the timing analysis did not satisfy the setup slack of DATA[0] to DATA[4].

In addition, I posted it once, but it was not reflected, so I posted it again with the same content.

Please pardon any duplication.

Sorry for the inconvenience, but thank you in advance.

that's all