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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Constraints on DDR signals

It would be helpful if you could teach me how to give constraints to the DDR signal from the ADC. The conditions are as follows. 　CLK　: 200MHz 　DATA resolution: 14bit 　Signal level: LVDS 　C...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Sir,


Thank you for submitting your question in Intel Community.


I may need more information regarding to this issue.

Can you provide the timing analysis report here? Or can you share a design that can replicate the issue?


Also, can you provide the EMIF IP setting together with memory datasheet that you used to configure the EMIF IP?


Regards,

Adzim


  • Yamada1's avatar
    Yamada1
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Thank you for your response.

    We are very sorry, but please refrain from providing reports.

    Therefore, it would be helpful if you could teach us how to describe the constraints when performing DDR constraints instead of the numerical values listed.

    We apologize for the inconvenience, but thank you.

    that's all