Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorConstraints on DDR signals
It would be helpful if you could teach me how to give constraints to the DDR signal from the ADC.
The conditions are as follows.
CLK : 200MHz
DATA resolution: 14bit
Signal level: LVDS
C...
Yamada1Occasional Contributor
Occasional ContributorThe other day, I stated that it would be difficult to provide the report, but I have received internal approval, so I am attaching the report file.
I couldn't attach it if it was .rep, so I made it .txt.
In addition, the signal names CLK and DATA in the question are ADC_CLK and ADC_DATA on the report file.
It would be helpful if you could teach me something.
