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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Constraints on DDR signals

It would be helpful if you could teach me how to give constraints to the DDR signal from the ADC. The conditions are as follows. 　CLK　: 200MHz 　DATA resolution: 14bit 　Signal level: LVDS 　C...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


May I know which IP that you used in the design?


Can I get the timing report for the failing path?

Can you export from the timing analyzer?


Regards,

Adzim